Ujwal Shyam Kantimohanthy
Engineering student building reliable web systems, evidence-grounded AI tools and network experiments.
Rome, Italy
Reviewed: 11 Nov 2026
Education
BSc in Engineering Sciences — University of Rome Tor Vergata
Undergraduate student focusing on networking, systems engineering, and computer science foundations. Bachelor thesis (in progress): wireless mesh networks and TV White Space spectrum for rural and obstructed terrain.
Experience & Research
Student Fellow · UNIVERSEH Student Fellowship (8-university European space consortium)
Sep 2025Participated in eight-university European consortium student fellowship exploring space-sector fundamentals.
Research Collaborator (DASER-Net) · INFERENCE Lab
Since Aug 2026Real-corpus CREMA-D ingestion, audio integrity checks, and speaker-disjoint split generation for cross-corpus speech emotion recognition.
Web Development Intern · Zidio Development (Bengaluru, hybrid)
Since Aug 2026Full-stack development on LOOP, a multi-tenant feedback intelligence demo with CSV formula escaping, RBAC, and grounded Q&A.
Website Diagnostics Audit · ZiShop (separate organisation from Zidio Development)
Sep 2026Diagnosed UX and technical reliability gaps on the public ZiShop storefront and delivered a prioritized written remediation report to founders.
Arylax Labs · Independent Lab Umbrella
Self-initiatedUmbrella identity grouping independent protocol observability and verification work (including DEVAN and the RFC 1035 iterative DNS trace).
Selected Technical Projects
LOOP — Customer feedback intelligence · Zidio Development internship
Submitted · DemoBuilt CSV/API ingestion with formula-injection escaping, four-role permission boundaries, time-window trend detection, and Ask LOOP grounded Q&A.
DASER-Net — Cross-corpus speech emotion recognition · INFERENCE Lab
Ongoing · ResearchEngineered the real CREMA-D audio ingestion validation, frozen speaker-disjoint splits, and global speaker ID namespace so evaluation stays leak-free.
DEVAN — Evidence ledger & static-first engineering portfolio · Personal / Arylax Labs
In progress · SystemDesigned UJ.OS architecture, strict state derivation (ENCOUNTERED -> STUDIED -> IMPLEMENTED -> TESTED), DNS iterative resolution proof, and static-export ledger.
Wireless Mesh + TV White Space — BSc Engineering Sciences Thesis · University of Rome Tor Vergata
Ongoing · Draft under reviewBuilt MATLAB terrain mesh propagation simulations and incumbent-aware TVWS spectrum sharing models placing relays along ridgelines and valley entrances.
CineForge AI Pro — Supporting work · IBM SkillsBuild AI Builders Challenge submission
Completed · Team submissionConnected Python script parsing, structured JSON extraction prompts, and scene segmentation pipelines for the July 2026 team submission.
Leadership & Presentations
- OGV Team Lead (AIESEC Roma Tre, Jan – Mar 2025) — Led an Outgoing Global Volunteer operations team at AIESEC Roma Tre.
- Events Lead (EuroTech Federation, Since Sep 2026) — First point of contact for inbound student engineering event proposals; structuring intake and review workflows.
- Speaker · Building a Sustainable Space Economy (Sustainable Space Conference, University of Rome Tor Vergata, Sep 2026) — Student presentation examining trade-offs between commercial space growth and orbital sustainability.